The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 2021

Filed:

May. 29, 2020
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Kiran Ravi Seth, Morrisville, NC (US);

Yusuf Cagatay Tekmen, Raleigh, NC (US);

Rodney Wayne Smith, Raleigh, NC (US);

Shivam Priyadarshi, Morrisville, NC (US);

Vignyan Reddy Kothinti Naresh, Redmond, WA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 11/14 (2006.01); G06F 8/41 (2018.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/30101 (2013.01); G06F 8/441 (2013.01); G06F 9/30047 (2013.01); G06F 9/30079 (2013.01); G06F 9/3855 (2013.01); G06F 11/1471 (2013.01); G06F 2201/84 (2013.01);
Abstract

A register mapping circuit for recovering a register mapping state associated with a flushed instruction by traversing ROB entries from a snapshot of another register mapping state. The register mapping circuit includes a ROB control circuit, a snapshot circuit, and a register rename recovery circuit (RRRC). The ROB control circuit allocates ROB entries to instructions entering a processor pipeline, including a target ROB entry allocated to a target instruction and other ROB entries allocated to other instructions. The snapshot circuit captures snapshots of logical register-to-physical register mapping states in the rename map table in association with a subset of instructions that could be flushed. If the target instruction is flushed, the RRRC restores the rename map table register mapping state corresponding to the target instruction based on a snapshot in a ROB entry allocated to another instruction, and traverses register mapping updates in the intervening ROB entries.


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