The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 13, 2021

Filed:

Apr. 03, 2020
Applicant:

Lipac Co., Ltd., Seoul, KR;

Inventor:

Sang Don Lee, Guri-si, KR;

Assignee:

Lipac Co., Ltd., Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/42 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/16 (2006.01); H01L 23/29 (2006.01); H01L 23/552 (2006.01);
U.S. Cl.
CPC ...
G02B 6/423 (2013.01); G02B 6/4206 (2013.01); G02B 6/428 (2013.01); G02B 6/4242 (2013.01); G02B 6/4256 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 24/48 (2013.01); H01L 25/167 (2013.01); G02B 6/4214 (2013.01); G02B 6/4284 (2013.01); H01L 23/293 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/552 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/05599 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/18 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/24195 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/48235 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/12041 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/12043 (2013.01); H01L 2924/15153 (2013.01); H01L 2924/1815 (2013.01);
Abstract

A semiconductor package including: a chip having a first surface and a second surface; a mold configured to encapsulate the chip; a vertical conductive channel electrically connected to a pad formed on the second surface of the chip while passing through the mold; a wiring pattern electrically connected to a pad formed on the first surface of the chip and configured to perform electrical connection in the package; an optical device arranged on a surface of the semiconductor package to be electrically connected to the vertical conductive channel; and an external connection terminal configured to electrically connect the semiconductor package to the outside.


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