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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11056501 B1

PDFFull Text
Date of Patent:
Jul. 06, 2021

Filed:

Feb. 26, 2018

Three-dimensional nand memory device with source line comprising metallic and semiconductor layers

Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Hideo Wada, Yokkaichi Mie, JP;

Hideto Takekida, Nagoya Aichi, JP;

Assignee:

TOSHIBA MEMORY CORPORATION, Tokyo, JP;

Attorney:

Kim & Stewart LLP

Primary Examiner:

Marcos D Pizarro

Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 29/10 (2006.01); H01L 27/11568 (2017.01); H01L 27/11573 (2017.01); H01L 23/528 (2006.01); H01L 27/11575 (2017.01); H01L 21/822 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 27/1157 (2017.01); H01L 27/1158 (2017.01); H01L 27/112 (2006.01); H01L 27/06 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/76805 (2013.01); H01L 21/76877 (2013.01); H01L 21/8221 (2013.01); H01L 21/823475 (2013.01); H01L 23/528 (2013.01); H01L 23/5283 (2013.01); H01L 27/0688 (2013.01); H01L 27/1128 (2013.01); H01L 27/1157 (2013.01); H01L 27/1158 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 29/1037 (2013.01); H01L 23/5226 (2013.01);
Abstract

According to an embodiment, a memory device comprises a conductive layer containing a metal, a semiconductor layer on the conductive layer, electrode layers stacked on the semiconductor layer in a stacking direction, a semiconductor pillar penetrating the electrode layers in the stacking direction and electrically connected to the semiconductor layer, and a charge trap layer between the electrode layers and the semiconductor pillar. The conductive layer has a recess or a through-hole below the semiconductor pillar.

Find Patent Forward Citations

Wada, Hideo. (2021). Three-dimensional nand memory device with source line comprising metallic and semiconductor layers (U.S. Patent No. 11056501). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11056501

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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