The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2021

Filed:

Feb. 21, 2020
Applicant:

University of Florida Research Foundation, Incorporated, Gainesville, FL (US);

Inventors:

Domenic J. Forte, Gainesville, FL (US);

Bicky Shakya, San Diego, CA (US);

Haoting Shen, Verdi, NV (US);

Mark M. Tehranipoor, Gainesville, FL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/00 (2006.01); H01L 21/8238 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 23/573 (2013.01); H01L 21/76831 (2013.01); H01L 21/823807 (2013.01); H01L 21/823871 (2013.01); H01L 23/5226 (2013.01); H01L 27/092 (2013.01);
Abstract

Integrated circuit (IC) camouflaging has emerged as a promising solution for protecting semiconductor intellectual property (IP) against reverse engineering. The cell camouflaging covert gate leverages doping and dummy contacts to create camouflaged cells that are indistinguishable from regular standard cells under modern imaging techniques. A comprehensive security analysis of the covert gate shows that it achieves high resiliency against SAT and test-based attacks at very low overheads. Models are derived to characterize the covert cells, and metrics are developed to incorporate them into a gate-level design. Simulation results of overheads and attacks are presented on benchmark circuits.


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