The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2021

Filed:

Aug. 31, 2018
Applicant:

Csmc Technologies Fab2 Co., Ltd., Jiangsu, CN;

Inventors:

Lihui Gu, Wuxi New District, CN;

Sen Zhang, Wuxi New District, CN;

Congming Qi, Wuxi New District, CN;

Assignee:

CSMC TECHNOLOGIES FAB2 CO., LTD., Wuxi New District, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/76 (2006.01); H01L 21/8249 (2006.01); H01L 27/06 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8249 (2013.01); H01L 21/823418 (2013.01); H01L 21/823493 (2013.01); H01L 27/0255 (2013.01); H01L 27/0259 (2013.01); H01L 27/06 (2013.01); H01L 29/739 (2013.01); H01L 29/78 (2013.01); H01L 29/7835 (2013.01);
Abstract

An integrated circuit chip and a manufacturing method therefor, and a gate drive circuit, the integrated circuit chip comprising: a semiconductor substrate (), a high voltage island () being formed in the semiconductor substrate (); a high voltage junction terminal (), the high voltage junction terminal () surrounding the high voltage island (), a depletion type MOS device (N) being formed on the high voltage junction terminal (), a gate electrode and a drain electrode of the depletion type MOS device (N) being short connected, and a source electrode of the depletion type MOS device (N) being connected to a high side power supply end (VB) of the integrated circuit chip; and a bipolar transistor (Q), a collector electrode of the bipolar transistor (Q) being short connected to the substrate and being connected to a low side power supply end (VCC) of the integrated circuit chip, an emitter of the bipolar transistor (Q) being connected to a gate electrode of the depletion type MOS device (N).


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