The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2021

Filed:

Mar. 04, 2019
Applicant:

Nippon Telegraph and Telephone Corporation, Tokyo, JP;

Inventors:

Hiroaki Katsurai, Musashino, JP;

Naoki Miura, Musashino, JP;

Hiroyuki Fukuyama, Musashino, JP;

Hideyuki Nosaka, Musashino, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 27/02 (2006.01); H03K 5/13 (2014.01); H03M 1/12 (2006.01);
U.S. Cl.
CPC ...
G11C 27/02 (2013.01);
Abstract

A track-and-hold circuit with a high sampling rate and reduced power consumption is provided. A track-and-hold circuit performing switching between a track mode in which a data signal that is equivalent to an input data signal is output and a hold mode in which a data signal which is input at a time of switching from the track mode to the hold mode is held and output, by using a clock signal, such that only the data signal in the hold mode is output, the track-and-hold circuit including: two sampling circuits configured to be connected in parallel to an input of the data signal and receive an in-phase data signal; a clock circuit configured to input a clock signal, which has a phase opposite to a phase of a clock signal input to one of the two sampling circuits, to the other of the two sampling circuits; and a multiplexer circuit configured to select and output a data output of either one of the two sampling circuits that is in the hold mode, by using the clock signal.


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