The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2021

Filed:

Oct. 12, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Pritish Narayanan, San Jose, CA (US);

Scott C Lewis, Essex Junction, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/54 (2006.01); G06N 3/063 (2006.01); H01L 27/24 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 11/54 (2013.01); G06N 3/0635 (2013.01); G11C 13/003 (2013.01); G11C 13/004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); H01L 27/2463 (2013.01);
Abstract

A system and method are shown for both forward and reverse read operations in a neuromorphic crossbar array that is part of an artificial neural network (ANN). During a forward read operation, a plurality of neuron activations are encoded into a pulse width drive array word line that gates a cell access transistor. A source-follower transistor is biased at a source follower voltage (VRDP) and a column voltage node (BLV) is held at read voltage (VREAD). During a reverse read operation, the cell access transistor operates as another source follower by: encoding a neuron error signal into the column voltage node (BLV), driving a gate line of the cell access transistor to the source follower voltage (VRDP), and holding an intermediate node between the cell access transistor of (a) and the source-follower transistor of (b) at the read voltage (VREAD).


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