The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2021

Filed:

Feb. 24, 2020
Applicant:

Kioxia Corporation, Minato-ku, JP;

Inventors:

Takuto Tanaka, Yokkaichi, JP;

Takeo Mori, Yokkaichi, JP;

Takashi Terada, Yokkaichi, JP;

Takamichi Tsuchiya, Yokkaichi, JP;

Assignee:

Kioxia Corporation, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01); H01L 27/11582 (2017.01); H01L 27/11556 (2017.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
G11C 5/025 (2013.01); G11C 5/06 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes: a memory cell array including: a plurality of memory cells stacked above a substrate, and a plurality of word lines respectively coupled to gates of the plurality of memory cells and extending in a first direction; and a first film including a first area above the memory cell array and a second area different from the first area, and having a compressive stress higher than silicon oxide. In the first area, a plurality of first trenches extending in the first direction are aligned in a second direction that intersects the first direction. In the second area, a second trench in a mesh form is provided.


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