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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11055465 B1

PDFFull Text
Expired
Date of Patent:
Jul. 06, 2021

Filed:

Sep. 04, 2019

Fill techniques for avoiding boolean drc failures during cell placement

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

David Wolpert, Poughkeepsie, NY (US);

Timothy A. Schell, Cary, NC (US);

Michael Gray, Fairfax, VT (US);

Erwin Behnen, Austin, TX (US);

Robert Mahlon Averill, III, Wappingers Falls, NY (US);

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

Attorneys:

Cantor Colburn LLP

William Kinnaman

Primary Examiner:

Leigh M Garbowski

Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 30/39 (2020.01); G06F 111/20 (2020.01); G06F 115/08 (2020.01); G06F 119/22 (2020.01); G06F 119/02 (2020.01); G06F 119/18 (2020.01); G06F 117/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 30/30 (2020.01); G06F 30/39 (2020.01); G06F 2111/20 (2020.01); G06F 2115/08 (2020.01); G06F 2117/12 (2020.01); G06F 2119/02 (2020.01); G06F 2119/18 (2020.01); G06F 2119/22 (2020.01);
Abstract

Methods, systems and computer program products for avoiding Boolean DRC failures during cell placement are provided. Aspects include generating a semiconductor layout by filling a plurality of rows within a macro block with cells including functional cells and fill cells. Aspects also include modifying the semiconductor layout by removing one or more fill cells from the macro block to create a gap. Aspects also include examining a set of cells that border edges of the gap to identify one or more predicted rule violations. Based on the identified one or more predicted rule violations, aspects also include modifying the semiconductor layout to change a shape of the gap to avoid the one or more predicted rule violations.

Find Patent Forward Citations

Wolpert, David. (2021). Fill techniques for avoiding boolean drc failures during cell placement (U.S. Patent No. 11055465). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11055465

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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