Integrated circuit having lanes interchangeable between clock and data lanes in clock forward interface receiver

Abstract

An integrated circuit in a physical layer of a receiver is provided. The integrated circuit includes a multi-lane interface, a lane selection circuit and N sampling circuits. The multi-lane interface has N lanes. N is an integer greater than one. The lane selection circuit, coupled to the multi-lane interface, is configured to select M of the N lanes as M clock lanes, and output M signals on the M clock lanes respectively. M is a positive integer less than N. Remaining (N−M) lanes serve as (N−M) data lanes. The N sampling circuits are coupled to the multi-lane interface and the lane selection circuit. (N−M) of the N sampling circuits are coupled to the (N−M) data lanes respectively. Each of the (N−M) sampling circuits is configured to sample a signal on one of the (N−M) data lanes according to one of the M signals on the M clock lanes.