The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 06, 2021

Filed:

Jun. 18, 2018
Applicants:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Ati Technologies Ulc, Markham, CA;

Inventors:

Leonardo De Paula Rosa Piga, Austin, TX (US);

Samuel Naffziger, Ft. Collins, TX (US);

Ivan Matosevic, Markham, CA;

Indrani Paul, Austin, TX (US);

Assignees:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

ATI Technologies ULC, Markham, CA;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/324 (2019.01);
U.S. Cl.
CPC ...
G06F 1/324 (2013.01);
Abstract

A power management algorithm framework proposes: 1) a Quality-of-Service (QoS) metric for throughput-based workloads; 2) heuristics to differentiate between throughput and latency sensitive workloads; and 3) an algorithm that combines the heuristic and QoS metric to determine target frequency for minimizing idle time and improving power efficiency without any performance degradation. A management algorithm framework enables optimizing power efficiency in server-class throughput-based workloads while still providing desired performance for latency sensitive workloads. The power savings are achieved by identifying workloads in which one or more cores can be run at a lower frequency (and consequently lower power) without a significant negative performance impact.


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