The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 29, 2021

Filed:

Aug. 12, 2019
Applicant:

Security Together Corporation, Roseville, CA (US);

Inventors:

Anthony Joseph Vargas, Roseville, CA (US);

Christopher Robert Sharpe, San Jose, CA (US);

Assignee:

SECURITY TOGETHER CORPORATION, Roseville, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01); G06F 21/78 (2013.01); G06F 21/71 (2013.01); G06F 21/50 (2013.01); G06F 21/42 (2013.01);
U.S. Cl.
CPC ...
H04L 63/1441 (2013.01); G06F 21/42 (2013.01); G06F 21/50 (2013.01); G06F 21/71 (2013.01); G06F 21/78 (2013.01); H04L 63/1425 (2013.01);
Abstract

Systems and methods for providing security to an integrated circuit/processor and the processor cores in an endpoint device using a dynamic security architecture environment (DSAE) are disclosed. A security system is configured to provide security to a host endpoint device, the security system comprising: a processing unit including an Operational Processing Unit (OPU), an Input Processing Unit (IPU), and an Execution Processing Unit (EPU); logic modules in communication with the processing unit, the logic modules including an Input System, an Operational System, and an Execution System; and a host interface being configured to enable the Input System, the Operational System, and the Execution System to be coupled for data and control transmissions therebetween and coupled for data and control transmissions between the processing unit and a physical Processor Packing Unit (PPU) including at least one processor core, the PPU being configured to use different processor instruction sets, the Input System, the Operational System, and the Execution System being configured to present a different attack surface at different intervals within a period of time for the PPU, each different attack surface corresponding to the PPU executing a different processor instruction set, the processing unit, the logic modules, and the host interface being integrated together with the PPU on an integrated circuit of the host endpoint device.


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