Reducing the latency of a syndrome-based quasi-cyclic decoder

Abstract

Disclosed are devices, systems and methods for reducing the latency of a quasi-cyclic linear code decoder. An example method includes receiving a noisy codeword, the codeword having been generated from a quasi-cyclic linear code and provided to a communication channel prior to reception by the decoder; computing a syndrome based on the noisy codeword; generating a plurality of memory cell addresses, a first memory cell address being a function of the syndrome and subsequent memory cell addresses being within a predetermined address range of the function of the syndrome; reading, in a parallel manner to reduce the latency of the decoder, a plurality of error patterns from the plurality of memory cell addresses and computing a checksum for each of the plurality of error patterns; and determining, based on the checksum for each of the plurality of error patterns, a candidate version of the transmitted codeword.