The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 29, 2021

Filed:

Sep. 29, 2016
Applicant:

Osram Opto Semiconductors Gmbh, Regensburg, DE;

Inventors:

Alexander F. Pfeuffer, Regensburg, DE;

Dominik Scholz, Bad Abbach, DE;

Assignee:

OSRAM OLED GMBH, Regensburg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/38 (2010.01); H01L 33/00 (2010.01); H01L 33/30 (2010.01); H01L 33/40 (2010.01); H01L 33/44 (2010.01);
U.S. Cl.
CPC ...
H01L 33/382 (2013.01); H01L 33/0093 (2020.05); H01L 33/30 (2013.01); H01L 33/40 (2013.01); H01L 33/44 (2013.01); H01L 2933/0016 (2013.01);
Abstract

A method for producing a semiconductor chip and a semiconductor chip are disclosed. In an embodiment, the method includes providing a semiconductor layer sequence having a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer is formed as a p-conducting semiconductor region and the second semiconductor layer is formed as an n-conducting semiconductor region, or vice versa, forming at least one recess in the semiconductor layer sequence so that side surfaces of the first and second semiconductor layers are exposed, wherein the recess is multiple times wider than deep and applying an auxiliary layer for electrically contacting the second semiconductor layer, wherein the auxiliary layer at the side surfaces exposed.


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