The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 29, 2021

Filed:

Aug. 21, 2017
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Beijing Boe Display Technology Co., Ltd., Beijing, CN;

Inventors:

Lianjie Qu, Beijing, CN;

Jinchao Bai, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/84 (2006.01); H01L 29/786 (2006.01); H01L 27/32 (2006.01); H01L 29/66 (2006.01); H01L 51/52 (2006.01); H01L 51/56 (2006.01); H01L 33/42 (2010.01);
U.S. Cl.
CPC ...
H01L 29/78645 (2013.01); H01L 27/3276 (2013.01); H01L 29/6675 (2013.01); H01L 29/78648 (2013.01); H01L 29/78663 (2013.01); H01L 51/5237 (2013.01); H01L 51/56 (2013.01); H01L 27/3262 (2013.01); H01L 33/42 (2013.01); H01L 2251/305 (2013.01);
Abstract

A dual-gate thin film transistor, a manufacturing method thereof, an array substrate and a display device are provided. The dual-gate thin film transistor includes: a base substrate and a first gate, a first gate insulating layer, an active layer, a second gate insulating layer, a first electrode, a second electrode, a second gate and a connection electrode, formed on the base substrate. The second gate, the first electrode and the second electrode are formed on the same level. The first gate insulating layer includes a first via hole exposing a portion of the first gate, and the connection electrode is electrically connected with the second gate and is electrically connected with the first gate through the first via hole.


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