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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11049784 B1

PDFFull Text
Date of Patent:
Jun. 29, 2021

Filed:

Jun. 12, 2019

Semiconductor device for use in harsh media

Applicant:

Melexis Technologies NV, Tessenderlo, BE;

Inventor:

Appolonius Jacobus Van Der Wiel, Duisburg, BE;

Assignee:

MELEXIS TECHNOLOGIES NV, Tessenderlo, BE;

Attorney:

Workman Nydegger

Primary Examiner:

Stephen W Smoot

Int. Cl.
CPC ...
H01L 23/532 (2006.01); H01L 23/31 (2006.01); H01L 21/02 (2006.01); H01L 21/56 (2006.01); H01L 23/29 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 29/04 (2006.01); H01L 29/16 (2006.01); H01L 29/84 (2006.01); H01L 35/22 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3171 (2013.01); H01L 21/02271 (2013.01); H01L 21/56 (2013.01); H01L 21/76895 (2013.01); H01L 23/291 (2013.01); H01L 23/298 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53209 (2013.01); H01L 23/53257 (2013.01); H01L 23/53261 (2013.01); H01L 23/53271 (2013.01); H01L 29/04 (2013.01); H01L 29/16 (2013.01); H01L 29/84 (2013.01); H01L 35/22 (2013.01);
Abstract

A semiconductor device comprising a first and second doped semiconductor layer wherein the first layer is a monosilicon layer and the second layer is a polysilicon layer, an oxide layer covering the first and second layer, and an interconnect which electrically connects the first and second layer comprises a metal alloy which has a first part in contact with the first layer and a second part in contact with the second layer, wherein a part of the metal alloy between the first and the second part crosses over a sidewall of the second layer; at least one electronic component is formed in the first and/or second layer; the semiconductor device moreover comprises a stoichiometric passivation layer which covers the first and second layer and the oxide layer.

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