The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 29, 2021

Filed:

Mar. 24, 2020
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Pradeep Raj, Utter Pradesh, IN;

Rahul Sahu, Bangalore, IN;

Sharad Kumar Gupta, Bangalore, IN;

Chulmin Jung, San Diego, CA (US);

Assignee:

Qualcomm Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/12 (2006.01); G11C 11/4094 (2006.01); G11C 11/4091 (2006.01); G11C 11/4074 (2006.01); G11C 11/4097 (2006.01); G11C 7/10 (2006.01); G11C 11/412 (2006.01); G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4094 (2013.01); G11C 7/1096 (2013.01); G11C 7/12 (2013.01); G11C 11/4074 (2013.01); G11C 11/4091 (2013.01); G11C 11/4097 (2013.01); G11C 11/412 (2013.01); G11C 11/419 (2013.01);
Abstract

Certain aspects of the present disclosure are directed to a memory circuit. The memory circuit generally includes a memory cell coupled between a bit-line and a complementary bit-line. The memory circuit also includes a first n-type metal-oxide-semiconductor (NMOS) transistor configured to couple the bit-line to a write drive input during a write cycle of the memory circuit. The memory circuit also includes a second NMOS transistor configured to couple the complementary bit-line to a complementary write drive input during the write cycle, and a multiplexer circuit having a first p-type metal-oxide-semiconductor (PMOS) transistor coupled between a voltage rail and the bit-line or the complementary bit-line, the multiplexer circuit being configured to couple, via the first PMOS transistor, the bit-line or the complementary bit-line to the voltage rail during the write cycle.


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