The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 29, 2021

Filed:

Jun. 30, 2017
Applicant:

Western Digital Technologies, Inc., Irvine, CA (US);

Inventors:

Arthur Shulkin, Yavne, IL;

Alexander Kalmanovich, Jerusalem, IL;

Ariel Navon, Revava, IL;

David Rozman, Kiryat-Malakhi, IL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/08 (2006.01); G06F 3/06 (2006.01); G06N 3/04 (2006.01); G11C 11/56 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/28 (2006.01); G06F 11/00 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G06N 3/08 (2013.01); G06F 3/0616 (2013.01); G06F 3/0653 (2013.01); G06F 3/0679 (2013.01); G06F 11/008 (2013.01); G06N 3/04 (2013.01); G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G11C 16/10 (2013.01); G11C 16/28 (2013.01); G11C 16/3495 (2013.01); G11C 16/0483 (2013.01);
Abstract

Systems and methods are described for predicting an endurance of groups of memory cells within a memory device, based on current characteristics of the cells. The endurance may be predicted by processing historical information regarding operation of memory devices according to a machine learning algorithm, such as a neural network algorithm, to generate correlation information between characteristics of groups of memory calls at a first time and an endurance metric at a second time. The correlation information can be applied to current characteristics of a group of memory cells to predict a future endurance of that group. Operating parameters of a memory device may be modified at a per-block level based on predicted block endurances to increase the speed of a device, the longevity of a device, or both.


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