The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 29, 2021

Filed:

Apr. 08, 2020
Applicant:

Alibaba Group Holding Limited, Grand Cayman, KY;

Inventors:

Xin Long, Hangzhou, CN;

Jun Zhang, Hangzhou, CN;

Yongke Zhao, Hangzhou, CN;

Assignee:

Alibaba Group Holding Limited, Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/3215 (2019.01); G06F 8/654 (2018.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 11/14 (2006.01); G06F 13/42 (2006.01); G06F 21/73 (2013.01); G06F 21/76 (2013.01); G06F 30/343 (2020.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G06F 21/76 (2013.01); G01R 31/318533 (2013.01); G06F 1/3215 (2013.01); G06F 8/654 (2018.02); G06F 9/30098 (2013.01); G06F 9/3861 (2013.01); G06F 11/1441 (2013.01); G06F 13/4282 (2013.01); G06F 30/343 (2020.01); G06F 2213/0026 (2013.01); G06F 2221/2141 (2013.01);
Abstract

A device including a management logic unit and a user logic unit, where the management logic unit comprises a Peripheral Component Interconnect Express (PCIe) module, and the PCIe module comprises a first physical functional unit and a second physical functional unit. The first physical functional unit is configured to receive a user logic loading request initiated by the second physical functional unit, where the user logic loading request carries a user logic identifier; obtain a user logic file based on the user logic identifier; and burn the user logic file into the user logic unit via a PCIe configuration channel. The present disclosure solves the technical problem that an existing FPGA cannot be deployed in the cloud due to the need for connecting to a JTAG cable when being remotely configured or debugged.


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