The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 2021

Filed:

May. 24, 2019
Applicant:

The United States of America As Represented BY the Secretary of the Navy, Newport, RI (US);

Inventors:

Charles J Patrissi, Newport, RI (US);

Joseph H Fontaine, North Kingstown, RI (US);

Jian Tan, New York, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02J 7/00 (2006.01); H01M 10/00 (2006.01); H01M 50/20 (2021.01); G01R 31/382 (2019.01); H01M 10/42 (2006.01); H01M 10/0525 (2010.01); H02J 7/24 (2006.01);
U.S. Cl.
CPC ...
H01M 10/425 (2013.01); G01R 31/382 (2019.01); H01M 10/0525 (2013.01); H01M 50/20 (2021.01); H02J 7/24 (2013.01);
Abstract

A modified battery cell for simulating failure conditions includes a multiple layer electrical cell. A transistor having a source, a gate, and a drain is positioned in the cell. A controllable voltage source is provided, joined to the gate and source of the transistor. The transistor source is further joined to a first location within said electrical cell multiple layers, and the transistor drain is electrically joined to a second location within said electrical cell multiple layers. Voltage from the controllable voltage source can reduce resistance between said transistor source and said transistor drain for simulating a fault condition between the first location and the second location.


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