The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 2021

Filed:

Jan. 28, 2019
Applicant:

Hitachi Automotive Systems, Ltd., Hitachinaka, JP;

Inventors:

Shinichirou Wada, Tokyo, JP;

Yoichiro Kobayashi, Hitachinaka, JP;

Masato Kita, Hitachinaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H03K 17/687 (2006.01); G05F 3/26 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); G05F 3/262 (2013.01); H03K 17/6871 (2013.01);
Abstract

A semiconductor device obtains high current ratio accuracy by eliminating an influence of plasma charging using a MOS-type transistor in which a channel region is isolated and separated from a semiconductor substrate. In a current mirror circuit in which both of a well of a NMOS-type transistor that generates a bias and a well of a NMOS-type transistor that receives the bias are formed insulated and separated from a semiconductor substrate, a connection circuit is connected between gate electrodes and wells of NMOS-type transistors without through the semiconductor substrate, and the connection circuit makes the gate electrodes and the wells in an electrically short-circuited state during manufacturing of the current mirror circuit, and makes the gate electrodes and the wells in a disconnected state in at least one direction during a mounting operation.


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