The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 2021

Filed:

Apr. 24, 2018
Applicant:

Cisco Technology, Inc., San Jose, CA (US);

Inventors:

Matthew J. Traverso, Santa Clara, CA (US);

Sandeep Razdan, Burlingame, CA (US);

Ashley J. Maker, Pleasanton, CA (US);

Assignee:

Cisco Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/16 (2006.01); H01L 31/02 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 25/167 (2013.01); H01L 21/4846 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 31/02005 (2013.01); H01L 23/49816 (2013.01); H01L 24/16 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01);
Abstract

An optoelectronic assembly and methods of fabrication thereof are provided. The assembly includes a mold compound; a photonic integrated circuit (PIC) embedded in the mold compound, that has a face exposed from the mold compound in a first plane; an interposer embedded in the mold compound, that has a face exposed from the mold compound in the first plane (i.e., co-planar with the exposed face of the PIC); and an electrical integrated circuit (EIC) coupled to the exposed face of the PIC and the exposed face of the interposer, that establishes bridging electrical connections between the PIC and the interposer.


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