The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 2021

Filed:

Jan. 20, 2017
Applicant:

Sony Corporation, Tokyo, JP;

Inventor:

Susumu Hogyoku, Kanagawa, JP;

Assignee:

SONY CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/15 (2006.01); H05K 3/46 (2006.01); H01L 27/146 (2006.01); H05K 1/02 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/15 (2013.01); H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H01L 27/146 (2013.01); H01L 27/14618 (2013.01); H01L 27/14625 (2013.01); H01L 27/14627 (2013.01); H01L 27/14636 (2013.01); H05K 1/0274 (2013.01); H05K 3/4605 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/73204 (2013.01); H05K 2201/0108 (2013.01); H05K 2201/09072 (2013.01); H05K 2201/10121 (2013.01);
Abstract

The present technology relates to a semiconductor device and a manufacturing method, an imaging device, and an electronic apparatus that enable component mounting with high flatness at low cost. A semiconductor device includes: a core substrate: a multilayer wiring layer that includes a plurality of conductive layers and a plurality of insulating layers, and is formed on a surface of the core substrate; an opening that is formed in the multilayer wiring layer, and penetrates through at least the outermost insulating layer farthest from the core substrate among the plurality of insulating layers; and a mount element connected to a pad portion provided on a predetermined conductive layer located closer to the core substrate than the outermost conductive layer farthest from the core substrate among the plurality of conductive layers in the opening. The present technology can be applied to imaging devices.


Find Patent Forward Citations

Hogyoku, Susumu. (2021). Semiconductor device, manufacturing method, imaging device, and electronic apparatus for enabling component mounting with high flatness (U.S. Patent No. 11043436). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11043436

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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