The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 2021

Filed:

Feb. 01, 2018
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Arjunesh Namboothiri Madhavan, Bangalore, IN;

Akash Bangalore Srinivasa, Bangalore, IN;

Sujit Kumar Rout, Bangalore, IN;

Vikash, Bangalore, IN;

Gaurav Rattan Singla, San Jose, CA (US);

Vivek Nautiyal, Milpitas, CA (US);

Shri Sagar Dwivedi, San Jose, CA (US);

Jitendra Dasani, Cupertino, CA (US);

Lalit Gupta, Cupertino, CA (US);

Assignee:

Arm Limited, Cambridge, GB;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); H01L 29/94 (2006.01); H01L 27/11 (2006.01); G11C 7/10 (2006.01); G11C 7/18 (2006.01); G11C 8/16 (2006.01); G11C 7/12 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 7/1096 (2013.01); G11C 7/12 (2013.01); G11C 7/18 (2013.01); G11C 8/16 (2013.01); H01L 27/1116 (2013.01); H01L 29/94 (2013.01);
Abstract

Various implementations described herein are directed to an integrated circuit having memory circuitry with an array of bitcells. The integrated circuit may include read-write circuitry that is coupled to the memory circuitry to perform read operations and write operations for the array of bitcells. The integrated circuit may include write assist circuitry that is coupled to the memory circuitry and the read-write circuitry. The write assist circuitry may receive a control signal from the read-write circuitry. Further, the write assist circuitry may sense write operations based on the control signal and may drive the write operations for the array of bitcells.


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