The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 22, 2021
Filed:
Apr. 10, 2020
Applicant:
The Trustees of Princeton University, Princeton, NJ (US);
Inventors:
David Wentzlaff, Princeton Junction, NJ (US);
Fei Gao, Princeton, NJ (US);
Georgios Tziantzioulis, Princeton, NJ (US);
Assignee:
THE TRUSTEES OF PRINCETON UNIVERSITY, Princeton, NJ (US);
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 11/4094 (2006.01); G11C 29/00 (2006.01); G11C 11/4091 (2006.01); G11C 11/4076 (2006.01); H03K 19/21 (2006.01); H03K 19/23 (2006.01); G11C 11/408 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4094 (2013.01); G11C 11/4076 (2013.01); G11C 11/4085 (2013.01); G11C 11/4091 (2013.01); G11C 29/88 (2013.01); H03K 19/20 (2013.01); H03K 19/21 (2013.01); H03K 19/23 (2013.01);
Abstract
According to various embodiments, an in-memory computation system is disclosed. The system includes a dynamic random access memory (DRAM) module. The system further includes a memory controller configured to violate a timing specification for the DRAM module and activate multiple rows of the DRAM module in rapid succession to enable bit-line charge sharing.