The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 2021

Filed:

Oct. 04, 2017
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Hem C. Neema, San Jose, CA (US);

Sonal Santan, San Jose, CA (US);

Bin Ochotta, Mountain View, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 21/00 (2013.01); G06F 21/12 (2013.01); H04L 9/32 (2006.01); G06F 21/77 (2013.01); H04L 29/06 (2006.01); H04W 12/06 (2021.01); H04W 12/10 (2021.01);
U.S. Cl.
CPC ...
G06F 21/123 (2013.01); G06F 21/77 (2013.01); H04L 9/3234 (2013.01); H04L 63/0853 (2013.01); H04W 12/06 (2013.01); H04W 12/10 (2013.01);
Abstract

Embodiments herein describe techniques for validating binary files used to configure a hardware card in a computing system. In one embodiment, the hardware card (e.g., an FPGA) includes programmable logic which the binary file can configure to perform a specialized function. In one embodiment, multiple users can configure the hardware card to perform their specialized tasks. For example, the computing system may be server on the cloud that hosts multiple VMs or a shared workstation. Permitting multiple users to directly configure and use the hardware card may present a security risk. To mitigate this risk, the embodiments herein describe techniques for validating encrypted binary files.


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