The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 2021

Filed:

Nov. 19, 2019
Applicant:

Nokia Solutions and Networks Oy, Espoo, FI;

Inventors:

Peter Winzer, Aberdeen, NJ (US);

David Neilson, Old Bridge, NJ (US);

Po Dong, Morganville, NJ (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/42 (2006.01); G02B 6/02 (2006.01); G02B 6/34 (2006.01);
U.S. Cl.
CPC ...
G02B 6/4202 (2013.01); G02B 6/02042 (2013.01); G02B 6/34 (2013.01); G02B 6/4214 (2013.01); G02B 6/4216 (2013.01); G02B 6/4249 (2013.01); G02B 6/4274 (2013.01);
Abstract

An optical interconnect circuit for transmitting data between two or more electronic chips. In an example embodiment, the optical interconnect circuit comprises two or more photonic chips, each of which is vertically stacked with the corresponding electronic chip such that compact optical modulators and/or photodetectors of the photonic chip are in close proximity to the data sources/sinks of the corresponding electronic chip. Multi-core optical fibers and vertical coupling structures are used to provide multiple optical connections between different photonic chips. Advantageously, the provided capability to place optical modulators close to the data sources and to place photodetectors close to the data sinks can be used to reduce the amount of required electrical wiring. Optical-waveguide connections to the multi-core fibers can be used to allow for high density of optical conduits without spatially constraining the placement of data sources and/or data sinks on the electronic chips.


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