The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 2021

Filed:

Aug. 13, 2018
Applicant:

Inxpect S.p.a., Brescia, IT;

Inventors:

Filippo Parrini, Florence, IT;

Luca Salgarelli, Besana in Brianza, IT;

Michael Granski, Tel Aviv, IL;

Assignee:

INXPECTS.P.A., Brescia, IT;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01S 7/03 (2006.01); H03F 3/195 (2006.01); H03L 7/099 (2006.01); H03F 3/24 (2006.01); G01S 13/87 (2006.01);
U.S. Cl.
CPC ...
G01S 7/032 (2013.01); G01S 13/87 (2013.01); H03F 3/195 (2013.01); H03F 3/245 (2013.01); H03L 7/099 (2013.01); H03F 2200/451 (2013.01);
Abstract

A multiple scalable radar on chip (SROC) based system in a multi-array configuration; may include: a first SROC; and a second SROC. The first SROC may include a ramp generator, a fractional-N PLL synthesizer, a frequency multiplier, a power amplifier, 'Y' number of transmitter chains, 'Z' number of receiver chains, and a receiver section. The second SROC may include a ramp generator, a fractional-N PLL synthesizer, a frequency multiplier, a power amplifier, ‘Y’ number of transmitter chains, ‘Z’ number of receiver chains, and a receiver section. The ramp generator of the first SROC may be configured to drive the fractional-N PLL synthesizer of the second SROC. The fractional-N PLL synthesizer of the second SROC may be configured to produce radio frequency (RF) ramp signals to drive both the first and second SROCs. ‘Y’ and ‘Z’ may represent positive integers.


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