The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 15, 2021
Filed:
Dec. 26, 2018
Applicant:
Zeroplus Technology Co., Ltd., New Taipei, TW;
Inventor:
Sung-Hui Lin, Taipei, TW;
Assignee:
ZEROPLUS TECHNOLOGY CO., LTD., New Taipei, TW;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01); G06F 16/22 (2019.01); G06F 16/25 (2019.01); H04L 12/24 (2006.01); G06F 11/36 (2006.01); G01R 31/3177 (2006.01); G06F 11/25 (2006.01);
U.S. Cl.
CPC ...
H04L 69/22 (2013.01); G01R 31/3177 (2013.01); G06F 11/25 (2013.01); G06F 11/364 (2013.01); G06F 16/2282 (2019.01); G06F 16/258 (2019.01); H04L 41/22 (2013.01);
Abstract
A bus packet format displaying method for a logic analyzer is disclosed. The logic analyzer fetches at least one packet of a bus of an electronic device. A computer host divides a plurality of bits of a second packet section of the packet into a plurality of message partitions according to a predetermined format defined in advance. Each of the message partitions has a value. The computer host gives a message name to each of the message partitions corresponding to the values and displays the message names and the values fetched by the logic analyzer on an operating screen.