The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2021

Filed:

Feb. 05, 2020
Applicant:

Credo Technology Group Limited, Grand Cayman, KY;

Inventors:

Junqing Sun, Fremont, CA (US);

Haoli Qian, Fremont, CA (US);

Assignee:

CREDO TECHNOLOGY GROUP LIMITED, Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04B 17/21 (2015.01); H04B 17/14 (2015.01); H04L 12/28 (2006.01);
U.S. Cl.
CPC ...
H04B 17/14 (2015.01); H04B 17/21 (2015.01); H04L 12/2801 (2013.01);
Abstract

An illustrative integrated circuit and method providing on-chip jitter evaluation. One illustrative integrated circuit embodiment includes a digital receiver having a timing recovery circuit that determines a phase offset signal from estimated timing errors of previous sampling instants; and an on-chip memory that captures the phase offset signal, the on-chip memory being coupled to a processor that derives one or more jitter measurements from the phase offset signal. For initial calibration, the processor may configure the receiver for loop back operation, and thereafter the calibration values may enable evaluation of remote transmitter clock jitter.


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