The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2021

Filed:

Aug. 19, 2019
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Steven F. Schicht, Austin, TX (US);

William R. Weier, Austin, TX (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/04 (2006.01); H03K 3/00 (2006.01); H03K 3/027 (2006.01); H03K 19/17736 (2020.01); H03K 19/00 (2006.01); H03K 3/017 (2006.01);
U.S. Cl.
CPC ...
H03K 3/027 (2013.01); H03K 3/017 (2013.01); H03K 19/0016 (2013.01); H03K 19/1774 (2013.01);
Abstract

In various embodiments, a clock pulse generation circuit may include a combination circuit, a first set-reset (SR) latch, a second SR latch, and a pulse generator. The combination circuit may be configured to generate a set signal based on an external clock signal. The first SR latch may be configured to generate an internal clock signal based on the reset signal and the set signal. The second SR latch may be configured to generate the reset signal based on the external clock signal and a reset pulse signal. The pulse generator may be configured to generate the reset pulse signal based on the internal clock signal. As a result, the clock pulse generation circuit may be configured to prevent the set signal from being asserted when the reset signal is asserted.


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