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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11038095 B1

PDFFull Text
Date of Patent:
Jun. 15, 2021

Filed:

Jan. 31, 2018

Systems and methods for fabrication of superconducting integrated circuits

Applicant:

D-wave Systems Inc., Burnaby, CA;

Inventors:

Shuiyuan Huang, Eagan, MN (US);

Byong H. Oh, San Jose, CA (US);

Douglas P. Stadtler, Morgan Hill, CA (US);

Edward G. Sterpka, Brentwood, CA (US);

Paul I. Bunyk, New Westminster, CA;

Jed D. Whittaker, Vancouver, CA;

Fabio Altomare, North Vancouver, CA;

Richard G. Harris, North Vancouver, CA;

Colin C. Enderud, Vancouver, CA;

Loren J. Swenson, San Jose, CA (US);

Nicolas C. Ladizinsky, Burnaby, CA;

Jason J. Yao, San Ramon, CA (US);

Eric G. Ladizinsky, Manhattan Beach, CA (US);

Assignee:

D-WAVE SYSTEMS INC., Burnaby, CA;

Attorney:

Cozen O'Connor

Primary Examiner:

Thomas L Dickey

Int. Cl.
CPC ...
H01L 27/18 (2006.01); H01L 39/24 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 39/12 (2006.01);
U.S. Cl.
CPC ...
H01L 39/2406 (2013.01); H01L 21/76891 (2013.01); H01L 23/528 (2013.01); H01L 23/5223 (2013.01); H01L 23/5226 (2013.01); H01L 23/5227 (2013.01); H01L 23/53257 (2013.01); H01L 23/53285 (2013.01); H01L 27/18 (2013.01); H01L 39/12 (2013.01);
Abstract

Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

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