The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2021

Filed:

Mar. 22, 2019
Applicant:

Seiko Epson Corporation, Tokyo, JP;

Inventors:

Isamu Moriya, Chino, JP;

Atsushi Yamada, Nagoya, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 21/761 (2006.01); H01L 29/06 (2006.01); H03K 17/082 (2006.01); H02M 7/5387 (2007.01);
U.S. Cl.
CPC ...
H01L 27/0928 (2013.01); H01L 21/761 (2013.01); H01L 21/823878 (2013.01); H01L 21/823892 (2013.01); H01L 29/0646 (2013.01); H03K 17/0822 (2013.01); H01L 21/82385 (2013.01); H01L 21/823814 (2013.01); H02M 7/53871 (2013.01); H03K 2217/0027 (2013.01); H03K 2217/0045 (2013.01);
Abstract

An electronic circuit includes a noise source and an analog circuit and a logic circuit that may be adversely affected by noise. At least a portion of the analog circuit and the logic circuit is formed on a buried impurity layer whose conductivity is different from that of a substrate, and at least a portion of the periphery of that portion is surrounded by an impurity layer that is different from the substrate. Thus, propagation of the noise from the noise source is prevented.


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