The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2021

Filed:

Apr. 16, 2020
Applicant:

Century Technology (Shenzhen) Corporation Limited, Shenzhen, CN;

Inventors:

Yung-Fu Lin, New Taipei, TW;

Po-Liang Chen, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/02 (2006.01); H05K 3/10 (2006.01); H01L 21/48 (2006.01); H01L 21/027 (2006.01); H01L 21/683 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/486 (2013.01); H01L 21/0273 (2013.01); H01L 21/6835 (2013.01); H01L 23/4985 (2013.01); H01L 24/19 (2013.01); H01L 24/93 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01);
Abstract

A method for making a redistribution circuit structure provides a substrate and forms a peelable layer on the substrate. A metal layer is formed on a surface of the peelable layer, the metal layer including a controlling circuit including at least two spaced units. A first photoresist layer is formed on a portion of the surface of the peelable layer and an insulating layer is applied to completely cover the first photoresist layer and the controlling circuit. Through holes are defined in the insulating layer to partially expose the controlling circuit and a seed layer applied on the insulating layer. A block layer is laid to divide the seed layer into multiple sections and electroplating in each section on a portion of the seed layer is applied to form a plating layer with better uniformity of thickness across all sections.


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