The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2021

Filed:

Nov. 06, 2019
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Arvind Jain, San Diego, CA (US);

Anju George, Ernakulam, IN;

Swayam Pattnaik, Bhubaneswar, IN;

Assignee:

Qualcomm Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/56 (2006.01); G11C 29/48 (2006.01); G11C 29/14 (2006.01); G11C 29/32 (2006.01);
U.S. Cl.
CPC ...
G11C 29/56 (2013.01); G11C 29/14 (2013.01); G11C 29/32 (2013.01); G11C 29/48 (2013.01); G11C 2029/5602 (2013.01);
Abstract

Disclosed are methods and apparatus for securely accessing and testing a double data rate (DDR) memory device. The apparatus includes a first memory test access port (TAP) configured to enable or disable access to at least one double date rate (DDR) memory device, a second memory TAP configured to enable or disable access to at least one non-DDR memory device, and a test controller configured to test the at least one DDR memory device via the first memory TAP or test the at least one non-DDR memory device via the second memory TAP. In an aspect, at least one non-DDR memory device contains proprietary information. Accordingly, access to the at least one non-DDR memory device via the second memory TAP is disabled when access to the at least one DDR memory device via the first memory TAP is enabled.


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