The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2021

Filed:

Jan. 31, 2018
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Arun Kumar Shukla, Bangalore, IN;

Sharad Gupta, Bangalore, IN;

Silky Mohanty, Bhubaneswar, IN;

Athira Kanchiyil, Bangalore, IN;

Arunkumar Mani, Thirunelveli, IN;

Noor Mohamed, Thanjavur, IN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 16/10 (2006.01); G11C 7/10 (2006.01); G11C 11/56 (2006.01); G11C 5/14 (2006.01); G06F 12/02 (2006.01); G11C 29/52 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G06F 3/0604 (2013.01); G06F 3/065 (2013.01); G06F 3/0631 (2013.01); G06F 3/0644 (2013.01); G06F 3/0647 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 5/148 (2013.01); G11C 7/1015 (2013.01); G11C 11/56 (2013.01); G06F 12/0223 (2013.01); G06F 2212/205 (2013.01); G11C 11/5628 (2013.01); G11C 29/04 (2013.01); G11C 29/52 (2013.01); G11C 2211/5641 (2013.01);
Abstract

Apparatuses, systems, methods, and computer program products are disclosed for hybrid dual write. An apparatus includes a memory device comprising a plurality of single level cell blocks and a plurality of multi level cell blocks. An apparatus includes a hybrid writing component. A hybrid writing component includes a single level writing circuit that writes data to a plurality of single level cell blocks. A hybrid writing component includes a multi level writing circuit that copies data from a plurality of single level cell blocks to a plurality of multi level cell blocks. A hybrid writing component includes an allocation circuit that allocates a single level cell block of a plurality of single level cell blocks to a first stream in response to a multi level cell block of a plurality of multi level cell block being allocated to the first stream.


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