The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2021

Filed:

May. 21, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Charles J. Camp, Sugar Land, TX (US);

Timothy J. Fisher, Cypress, TX (US);

Aaron D. Fry, Richmond, TX (US);

Nikolas Ioannou, Zurich, CH;

Ioannis Koltsidas, Zurich, CH;

Roman Pletka, Uster, CH;

Sasa Tomic, Kilchberg, CH;

Andrew D. Walls, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/0855 (2016.01); G06F 12/0884 (2016.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0855 (2013.01); G06F 12/0246 (2013.01); G06F 12/0884 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/222 (2013.01); G06F 2212/608 (2013.01); G06F 2212/7202 (2013.01); G06F 2212/7207 (2013.01); G06F 2212/7208 (2013.01);
Abstract

A computer-implemented method, according to one embodiment, includes: retrieving a physical block address corresponding to a logic block address, extracting information from the physical block address, and performing a lookup operation in cache using the extracted information. A range check of the physical block address is further performed in response to the lookup operation succeeding, while data is read from the cache in response to the range check succeeding. An architecture of the cache supports separation of data streams, as well as parallel writes to different non-volatile memory channels. The cache architecture further supports pipelining of the parallel writes to different non-volatile memory planes. Moreover, the non-volatile memory controller is configured to perform a direct memory lookup in the cache based on a physical block address.


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