The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2021

Filed:

Dec. 03, 2018
Applicant:

Mentor Graphics Corporation, Wilsonville, OR (US);

Inventors:

Sanjay Pillay, Aust, TX (US);

Arun Kumar Gogineni, Cedar Park, TX (US);

Srikanth Rengarajan, Austin, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/26 (2006.01); G06F 30/15 (2020.01); G06F 30/20 (2020.01); G06F 30/30 (2020.01); G06F 30/3312 (2020.01);
U.S. Cl.
CPC ...
G06F 11/261 (2013.01); G06F 30/15 (2020.01); G06F 30/20 (2020.01); G06F 30/30 (2020.01); G06F 30/3312 (2020.01);
Abstract

This application discloses a computing system implementing a functional safety validation tool to simulate an integrated circuit design with a stimulus vector. The computing system can inject a fault at a first node of the simulated integrated circuit design, which prompts alarm logic to trigger indicating a detection of the injected fault. The computing system, in response to the triggering of the alarm logic, can initiate back-propagation to identify which intermediate nodes of the simulated integrated circuit design, located between the first node and the alarm logic, have fault values that prompt the alarm logic to trigger. The computing system can generate a fault coverage presentation identifying a diagnostic coverage of the alarm logic for the stimulus vector based on when the alarm logic.


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