The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 15, 2021
Filed:
Oct. 04, 2019
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventor:
Joon-Woo Kim, Seoul, KR;
Assignee:
SK hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G06F 11/20 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01); G06F 12/10 (2016.01); G11C 5/04 (2006.01); G06F 12/02 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2094 (2013.01); G06F 11/1048 (2013.01); G06F 11/1068 (2013.01); G06F 12/0292 (2013.01); G06F 12/10 (2013.01); G11C 5/04 (2013.01); G11C 29/52 (2013.01); G06F 2201/805 (2013.01); G06F 2201/82 (2013.01); G06F 2212/1032 (2013.01); G11C 29/70 (2013.01);
Abstract
A memory module may include a first memory module comprising a plurality of first memory devices each having an extra memory region, a second memory module comprising a plurality of second memory devices each having an extra memory region, and a control logic suitable for writing/reading data to/from the first memory devices, wherein the control logic writes/reads target data to be transferred to/from a third memory device having an error among the first memory devices, to/from the extra memory regions of the second memory devices.