The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2021

Filed:

Jun. 11, 2019
Applicant:

Hitachi, Ltd., Tokyo, JP;

Inventors:

Atsuki Kiuchi, Tokyo, JP;

Tazu Nomoto, Tokyo, JP;

Yasuo Bakke, Tokyo, JP;

Takahiro Ogura, Tokyo, JP;

Assignee:

HITACHI, LTD., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06Q 10/08 (2012.01); G06F 9/38 (2018.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3885 (2013.01); G06F 9/30094 (2013.01); G06F 9/3877 (2013.01); G06Q 10/08 (2013.01); G06F 9/50 (2013.01); G06Q 10/087 (2013.01);
Abstract

A parallel distributed processing control system used in production distribution planning includes: a storage unit storing step information of steps constituting a production distribution process of a product, CPU information of CPUs that calculate a value of a simulation result for the step, and a constraint value in the production distribution process; a divided model generation unit generating a divided model by grouping the steps; a CPU allocation unit allocating the divided model to the plurality of CPUs; an engine execution unit enabling the CPU to calculate the value for the step constituting the divided model; and a constraint monitoring unit determining whether the value satisfies a condition specified by the constraint value. An output information generation unit generates result information using the value satisfying the condition; and the CPU allocation unit allocates the divided model so that processing loads of the plurality of CPUs are equalized.


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