The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 15, 2021

Filed:

Mar. 27, 2020
Applicants:

Hefei Boe Display Technology Co., Ltd., Anhui, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Yuntian Zhang, Beijing, CN;

Peng Jiang, Beijing, CN;

Ke Dai, Beijing, CN;

Jingang Liu, Beijing, CN;

Lihui Han, Beijing, CN;

Zhonghou Wu, Beijing, CN;

Chunxu Zhang, Beijing, CN;

Mengmeng Li, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1362 (2006.01); G09G 3/34 (2006.01); G02F 1/1333 (2006.01); G02F 1/13357 (2006.01); G02F 1/1368 (2006.01); G02F 1/1335 (2006.01);
U.S. Cl.
CPC ...
G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); G02F 1/133345 (2013.01); G02F 1/133603 (2013.01); G02F 1/136209 (2013.01); G09G 3/3426 (2013.01); G02F 1/133612 (2021.01);
Abstract

An array substrate includes a substrate, at least one first light-shielding layer disposed above the substrate, semiconductor retention layers disposed on a side of the at least one first light-shielding layer facing away from the substrate, and data lines disposed on a side of the plurality of semiconductor retention layers facing away from the at least one first light-shielding layer. One first light-shielding layer of the at least one first light-shielding layer is disposed between one semiconductor retention layer of the semiconductor retention layers and the substrate, and an orthographic projection of the first light-shielding layer on the substrate covers an orthographic projection of the semiconductor retention layer on the substrate. The data lines are in one-to-one correspondence with the semiconductor retention layers, and an orthographic projection of each data line on the substrate overlaps with an orthographic projection of a corresponding semiconductor retention layer on the substrate.


Find Patent Forward Citations

Loading…