The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2021

Filed:

Jun. 28, 2018
Applicants:

Stmicroelectronics Application Gmbh, Ascheim-Dornach, DE;

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Roberto Colombo, Munich, DE;

Guido Marco Bertoni, Bernareggio, IT;

William Orlando, Peynier, FR;

Roberta Vittimani, Agrate Brianza, IT;

Assignees:

STMICROELECTRONICS S.R.L., Agrate Brianza, IT;

STMICROELECTRONICS APPLICATION GMBH, Ascheim-Dornach, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 9/08 (2006.01); G06F 13/36 (2006.01); H04L 9/14 (2006.01); H04L 9/32 (2006.01);
U.S. Cl.
CPC ...
H04L 9/0819 (2013.01); G06F 13/36 (2013.01); H04L 9/0897 (2013.01); H04L 9/14 (2013.01); H04L 9/3239 (2013.01); H04L 2209/38 (2013.01);
Abstract

A hardware secure module includes a processing unit and a cryptographic coprocessor. The cryptographic coprocessor includes a key storage memory; a hardware key management circuit configured to store a first cryptographic key in the key storage memory; a first interface configured to receive source data to be processed; a second interface configured to receive the first cryptographic key from the processing unit for storing in the key storage memory; a hardware cryptographic engine configured to process the source data as a function of the first cryptographic key stored in the key storage memory; and a third interface configured to receive a second cryptographic key. The hardware secure module further includes a non-volatile memory configured to store the second cryptographic key; and a hardware configuration module configured to read the second cryptographic key from the non-volatile memory and send the second cryptographic key to the third interface.


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