The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2021

Filed:

Sep. 03, 2020
Applicant:

Nuvoton Technology Corporation, Hsinchu, TW;

Inventors:

Yuan-Po Cheng, Hsinchu, TW;

Pao-Shu Chang, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/038 (2006.01);
U.S. Cl.
CPC ...
H03K 3/038 (2013.01);
Abstract

A clock multiplier is provided. The clock multiplier includes a delay line, an output clock generator, and a delay controller. The delay line receives an input clock and delays the input clock according to a selection signal group with multiple bits to provide a plurality of delayed clocks and a feedback clock. The output clock generator performs a logic operation on the input clock and a portion of the delayed clocks to generate an output clock. A frequency of the output clock is an integer multiple of a frequency of the input clock. The delay controller adjusts the selection signal group according to a timing difference between the input clock and the feedback clock, so that a transition point of the feedback clock approaches a transition point of the input clock.


Find Patent Forward Citations

Cheng, Yuan-Po. (2021). Clock multiplier (U.S. Patent No. 11031924). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11031924

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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