The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2021

Filed:

Feb. 27, 2020
Applicant:

Lapis Semiconductor Co., Ltd., Kanagawa, JP;

Inventor:

Taku Shibaguchi, Miyagi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); H01L 27/11526 (2017.01); G11C 16/26 (2006.01); H01L 27/11521 (2017.01); H01L 29/08 (2006.01); H01L 29/423 (2006.01); G11C 16/04 (2006.01); H01L 29/66 (2006.01); G11C 16/10 (2006.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 21/3105 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11526 (2013.01); G11C 16/0408 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); H01L 27/11521 (2013.01); H01L 29/0847 (2013.01); H01L 29/42324 (2013.01); H01L 29/66568 (2013.01); H01L 29/66825 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02238 (2013.01); H01L 21/02255 (2013.01); H01L 21/02271 (2013.01); H01L 21/02274 (2013.01); H01L 21/26513 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 21/76224 (2013.01); H01L 29/40114 (2019.08);
Abstract

A semiconductor device includes a semiconductor substrate, and a nonvolatile memory cell disposed on the semiconductor substrate. The nonvolatile memory cell includes a field-effect transistor for data writing, and a field-effect transistor for data readout that is adjacent to the field-effect transistor for data writing. Each of the field-effect transistor for data writing and the field-effect transistor for data readout includes a gate insulating film formed on the semiconductor substrate, a floating gate formed on the gate insulating film, and diffusion layers configuring a source region and a drain region on respective sides of the floating gate viewed in the thickness direction of the semiconductor substrate. The thickness of the gate insulating film of the field-effect transistor for data readout, and the thickness of the gate insulating film of the field-effect transistor for data writing, are different.


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