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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11031392 B1

PDFFull Text
Date of Patent:
Jun. 08, 2021

Filed:

Dec. 05, 2019

Integrated circuit device having a work function control layer with a step portion located on an element isolation layer

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Yongho Jeon, Suwon-si, KR;

Sekoo Kang, Suwon-si, KR;

Sungwoo Myung, Suwon-si, KR;

Keunhee Bai, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;

Attorney:

Muir Patent Law, PLLC

Primary Examiner:

Younes Boulghassoul

Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/49 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/786 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 21/033 (2006.01); H01L 21/84 (2006.01); H01L 21/28 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/0332 (2013.01); H01L 21/0334 (2013.01); H01L 21/28088 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 21/845 (2013.01); H01L 27/0924 (2013.01); H01L 29/0673 (2013.01); H01L 29/42368 (2013.01); H01L 29/42372 (2013.01); H01L 29/42376 (2013.01); H01L 29/42392 (2013.01); H01L 29/4966 (2013.01); H01L 29/512 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/78696 (2013.01); H01L 27/1211 (2013.01); H01L 29/0653 (2013.01);
Abstract

An integrated circuit device includes a first fin-type active area and a second fin-type active area protruding from a substrate and extending in a first direction, an element isolation layer between the first and second fin-type active areas on the substrate, first semiconductor patterns being on a top surface of the first fin-type active area and having channel areas, second semiconductor patterns being on a top surface of the second fin-type active area and having channel areas, a first gate structure extending on the first fin-type active area in a second direction and including a first work function control layer surrounding the first semiconductor patterns and comprising a step portion on the element isolation layer, and a second gate structure extending on the second fin-type active area in the second direction and including a second work function control layer surrounding the second semiconductor patterns.

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