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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11031385 B1

PDFFull Text
Date of Patent:
Jun. 08, 2021

Filed:

Dec. 23, 2019

Standard cell for removing routing interference between adjacent pins and device including the same

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jae-Woo Seo, Seoul, KR;

Jin Tae Kim, Daejeon, KR;

Tae Joong Song, Seongnam-si, KR;

Hyoung-Suk Oh, Seoul, KR;

Keun Ho Lee, Hwaseong-si, KR;

Dal Hee Lee, Seoul, KR;

Sung We Cho, Hwaseong-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Gyeonggi-do, KR;

Attorney:

Harness, Dickey & Pierce, P.L.C.

Primary Examiner:

Jack Chiang

Assistant Examiner:

Aric Lin

Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 27/088 (2006.01); H01L 21/67 (2006.01); H01L 21/8234 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H03K 19/17736 (2020.01); H03K 19/17764 (2020.01); H01L 27/118 (2006.01); H01L 27/092 (2006.01); H03K 19/00 (2006.01); H03K 19/20 (2006.01); H03K 19/21 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); H01L 21/67138 (2013.01); H01L 21/823475 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/088 (2013.01); H01L 27/0886 (2013.01); H03K 19/17744 (2013.01); H03K 19/17764 (2013.01); H01L 27/092 (2013.01); H01L 2027/11875 (2013.01); H03K 19/0002 (2013.01); H03K 19/20 (2013.01); H03K 19/21 (2013.01);
Abstract

An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.

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