The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2021

Filed:

Mar. 15, 2019
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Rainer Pelzer, Wernberg, AT;

Fortunato Lopez, Unterhaching, DE;

Antonia Maglangit, Villach, AT;

Siti Amira Faisha Shikh Zakaria, Melaka, MY;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 21/768 (2006.01); H01L 21/48 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49513 (2013.01); H01L 21/4821 (2013.01); H01L 21/76876 (2013.01); H01L 23/49562 (2013.01); H01L 23/53238 (2013.01);
Abstract

A semiconductor device includes a semiconductor substrate, a power transistor formed in the semiconductor substrate, the power transistor including an active area in which one or more power transistor cells are formed, a first metal pad formed above the semiconductor substrate and covering substantially all of the active area of the power transistor, the first metal pad being electrically connected to a source or emitter region in the active area of the power transistor, the first metal pad including an interior region laterally surrounded by a peripheral region, the peripheral region being thicker than the interior region, and a first interconnect plate or a semiconductor die attached to the interior region of the first metal pad by a die attach material. Corresponding methods of manufacture are also described.


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