The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2021

Filed:

Apr. 20, 2020
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Nobuo Tsuboi, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8239 (2006.01); H01L 27/105 (2006.01); H01L 27/11 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8239 (2013.01); H01L 27/1104 (2013.01); H01L 27/1116 (2013.01); H01L 27/1203 (2013.01); H01L 27/1052 (2013.01); H01L 29/0696 (2013.01);
Abstract

To improve a reliability of a semiconductor device, a memory cell array is formed in a product region of an SOI substrate, and a test cell array is formed in a scribe region of the SOI substrate. A plurality of regions is formed in each of the memory cell array and the test cell array. The plurality of regions formed in the test cell array is the same configuration as the plurality of regions formed in the memory cell array. A plurality of plugs is formed in the plurality of regions, respectively. Also, it can determine whether or not a leak path is occurred in the memory cell array, by inspecting whether or not a conduction between the plurality of plugs is confirmed.


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