The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 08, 2021
Filed:
Sep. 27, 2019
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventor:
Yasuhiko Akaike, Tokyo, JP;
Assignee:
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/50 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/495 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/4821 (2013.01); H01L 21/56 (2013.01); H01L 23/49513 (2013.01); H01L 24/83 (2013.01); H01L 24/85 (2013.01); H01L 24/92 (2013.01); H01L 23/293 (2013.01); H01L 23/3107 (2013.01); H01L 23/49582 (2013.01); H01L 24/05 (2013.01); H01L 24/45 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/45664 (2013.01); H01L 2224/83359 (2013.01); H01L 2224/85359 (2013.01); H01L 2224/92247 (2013.01);
Abstract
After a die bonding step, a wire bonding step is performed to electrically connect the plurality of pad electrodes and the plurality of leads of the semiconductor chip via a plurality of copper wires. A plating layer is formed on a surface of the lead, and a copper wire is connected to the plating layer in the wire bonding step. The plating layer is a silver plating layer. After the die bonding step, an oxygen plasma treatment is performed on the lead frame and the semiconductor chip before the wire bonding step, and then the surface of the plating layer is reduced.