The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2021

Filed:

May. 05, 2020
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventor:

Moon Sik Seo, Yongin-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/16 (2006.01); G11C 16/12 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/30 (2006.01);
U.S. Cl.
CPC ...
G11C 16/16 (2013.01); G11C 16/0433 (2013.01); G11C 16/08 (2013.01); G11C 16/12 (2013.01); G11C 16/24 (2013.01); G11C 16/30 (2013.01);
Abstract

There are provided a semiconductor memory and an operating method thereof. The semiconductor memory includes: a memory block including a plurality of pages; a peripheral circuit for performing a first erase operation, a program operation, and a second erase operation on the memory block in a write operation on the memory block; and control logic for controlling the peripheral circuit to perform the write operation. The control logic is configured to control the peripheral circuit to erase a plurality of memory cells included in the memory block to a pre-erase state having a threshold voltage higher than a threshold voltage of a target erase state in the first erase operation, and controls the peripheral circuit to erase some memory cells among the plurality of memory cells to the target erase state in the second erase operation.


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